Okay now I see EVGA has released the SR-X.
Very nice idea again, but this time I really dont see what went wrong here.
I'll start with what I see a REAL MESS UP in the design of this board.
We all know PCI-EX lane routing on our enthusiast systems has been a real struggle since the PCI-Express technology existed, allways having to find a solution to get more lanes to a single GPU or splitting them to multi GPUs.
Now before Socket R (2011) was released, the best we could get is 36 lanes from a x58 chipset, giving x16 / x16 OR x16 / x8 / x8.
Many other designs exist too, ranging from the NF790i to the NF200 bridges and Lucid, PLX and others... all trying to split and share lanes; nothing really good for high bandwith.
Release of the Socket R processors has finally unlocked what i've been waiting for years: 40 lanes per CPU, with 80lanes in a dual socket board !
Now lets see 5 "equivalent" boards to the SR-X, all sharing the SAME design and layout.
- Supermicro X9DAi:
Three (3) PCI Express 3.0 x16 slots (CPU1 Slot2/
CPU2 Slot4/CPU2 Slot6),
Three (3) PCI Express 3.0 x8 slots (CPU1 Slot1/
CPU1 Slot3/CPU2 Slot5),
- Supermicro X9DR3-LN4F+
Four (4) PCI Express 3.0 x16 slots (CPU1 Slot1/Slot3, CPU2 Slot4/Slot5),
One (1) PCI Express 3.0 x8 slot (CPU2 Slot6),
One (1) PCI Express 3.0x4 in x8 slot (CPU 1Slot2)
- Intel® Server Board S2600CO Family
-Slot 1: PCIe Gen II x4 electrical with x8 physical connector, routed from Intel Â® C600 Chipset, support half-length card
-Slot 2: PCIe Gen III x16 electrical with x16 physical connector, routed from CPU1, support full length card
-Slot 3: PCIe Gen III x16 electrical with x16 physical connector, routed from CPU2, support full length, double width card
-Slot 4: PCIe Gen III x8 electrical with x8 connector, routed from CPU2, support full length card; support Intel designed SAS RAID on Card (ROC) Module (PCIe slot form factor)
-Slot 5: PCIe Gen III x16 electrical with x16 connector, routed from CPU1, support full length, double width card
-Slot 6: PCIe Gen III x16 electrical with x16 connector, routed from CPU2, support half-length card, Intel designed PCIe riser card
- TYAN S7055 (S7055AGM3NR)
(4) PCI-E Gen3 x16 slots (slot #7, #5, #3, #1) / (1) PCI-E Gen2 x8 slots (slot #4)
- ASUS Z9PE-D16
Slot 5: PCI-E x16 slot, x16 Gen3 Link , from CPU 1 (Auto switch to x8 Link if slot 6 is occupied)
Slot 4: PCI-E x16 slot, x16 Gen3 Link, from CPU 2
Slot 3: PCI-E x16 slot, x16 Gen3 Link, from CPU 1
Slot 2: PCI-E x16 slot, x16 Gen3 Link, from CPU 2
Slot 6: PCI-E x16 slot, x8 Gen3 Link , from CPU 1
Slot 1: PCI-E x16 slot, x8 Gen3 Link, from CPU2
Many other boards share the same design, i just cant post them all here, but:
All use the C606 /C602 chipset,
Have about the same options like SAS/SATA,
Ok some dont have Integrated audio, but these are server boards,
They ALL have some kind of BMC controller and remote management.
NOW LETS COME BACK TO OUR SR-X.
Whats the huge difference?
I see a PLX bridge splitting some lanes, ****?? Why cant it use all those native CPU lanes? Isn't it a dual socket? Want to use only 1 CPU? Just buy a single socket MOBO !
I see PCI-Express 3.0 switches, 4 per slot. ****? I thought the CPU PCI-e controller is native 3.0... Do u see those switches on the server boards I mentioned above? NO. But they are REAL Native 3.0 !!
I see an "HPTX" form factor, witch is an odd form I dont understand why using it. Look at the server boards, they all use SSI-EEB form factor
(304.80 mm x 330.20 mm), just nice to fit in a case like mine without touching the drive backplanes...
Now all I think EVGA has to do is redesign the board, this is no real enthusiast board compared to those nice (but not red) server boards...
I want to buid a new rig soon, and if EVGA cant build a board using all the PCI-Ex lanes, they lost me. (being with eevga for years...)
I am planning to use:
2 GPUs Radeon HD7970 (Slot1 / slot 3)
1 Areca 2882ix-24 SAS 2.0 Gen2 Dual core for the 15K storage
1 PCI Ex SSD (maybe the IODRIVE2 DUO 1.2TB SLC)
1 Sound controller
Or maybe quad GPUs...
<message edited by servxtrem on Sunday, March 11, 2012 5:42 PM>